Design of Efficient Han-Carlson-Adder
نویسنده
چکیده
In digital VLSI systems binary addition is the most significance arithmetic function. To a great extent adders are used as DSP lattice filter where the ripple carry adders are substituted by the parallel prefix adder to reduce delay. The requirement of adder is that it is fast and it has area efficient and low power consumption. In this the parallel prefix adder is introduced as speculative HanCarlson adder for differ binary addition of the most significant arithmetic function. In this method has wider word length and the parallel prefix adder is replaced as speculative Han-Carlson adder is introduced as variety stages of Brent-Kung and Kogge-Stone adders reduces the complexity of adder design. The design of Verilog code is simulated using ModelSim and implemented in Xilinx.
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